Static Random Access Memory (SRAM) is a type of semiconductor memory. Data stored in an SRAM is retained as long as power remains applied, unlike dynamic RAM (DRAM) that needs to be periodically refreshed, read-only memory (ROM), or flash memory. SRAM is referred to as volatile memory since data is preserved only while power is continuously applied. SRAM provides faster access to data, but is more expensive than DRAM. SRAM is typically used for a computer's cache memory and as part of the random access memory digital-to-analog converter on a video card.
Random access means that locations in the memory are written to or read from in any order, regardless of the memory location that was last accessed. Each bit in a conventional SRAM device is stored on four transistors that form two cross-coupled inverters. Such a memory cell has two stable states which are used to denote a logic 0 and a logic 1. Two additional access transistors serve to control the access to the memory cell during read and write operations. As such, it typically takes six transistors to store one memory bit.
Access to each memory cell is enabled by a word line, which controls the two access transistors. The two access transistors control whether the memory cell is connected to one or both bit lines, which are used to transfer data during both read and write operations. Two bit lines are typically used to improve noise margins.
Three different operations are applied to a memory cell, a standby operation, a read operation, and a write operation. For the standby operation, if the word line is not asserted, the two access transistors disconnect the memory cell from the bit lines, and the two cross coupled inverters continue to reinforce each other as long as they are disconnected from the bit lines.
A read operation is initiated by pre-charging both the bit lines to a logical 1, then asserting the word line, thereby enabling both the access transistors. Then, the data stored in the two cross-coupled inverters is transferred to the bit lines. If the data stored in the memory cell is a logical 1, then a first bit line is discharged to a logical 0, and a second bit line is pulled to a logical 1. If the content of the memory cell is a logical 0, then the first bit line is pulled towards a logical 1 and the second bit line is discharged to a logical 0.
A write operation is initiated by applying the data value to be written to the bit lines. If the data value to be written is a logical 0, then a logical 0 is applied to the bit lines by setting the first bit line to a logical 1 and the second bit line to a logical 0. If the data value to be written is a logical 1, then the first bit line is set to a logical 0 and the second bit line is set to a logical 0. The word line is then asserted and the data value that is to be stored is latched by the two cross-coupled inverters. The bit line input-drivers are designed to be much stronger than the relatively weak transistors in the memory cell itself, so that the previous state of the cross-coupled inverters is easily overwritten. Careful sizing of the transistors in a SRAM cell is needed to ensure proper operation.
Conventional SRAMS perform one operation, either a read operation or a write operation, in one clock cycle. An SRAM receives one set of addresses and performs a first level, global predecode. Then, the predecoding lines within the SRAM distribute the predecode signals according to a decoding map. A second level decoding is performed locally on the predecoding signals to select a specific memory location. The read operation or the write operation is selected via a control pin. If the read operation is selected, then the data is read from the specific memory location via a data output pin. If the write operation is selected, then the data is written into the specific memory location via a data input pin.
Conventionally, a decoding signal is generated from an emulated self-timed pulse, which is triggered from the rising edge of an external clock. An emulation circuit generates the decoding signal by either emulating a minimum read pulse width or by emulating a minimum write pulse width. The read pulse width is wider than the write pulse width. The minimum cycle time is limited by the decoding signal pulse width and the time needed for bit-line level recovery.
FIG. 1 illustrates the waveforms associated with conventional SRAMS. An external clock signal is provided to the SRAM. The emulated self-timed pulse is triggered by the rising edge of the external clock signal. The decoding signal is generated from the self-timed pulse. A width of each pulse of the decoding signal is equal to a pulse width of the self-timed pulse. The pulse width corresponds to the amount of time required by the SRAM to perform the read operation or the write operation. The pulse width varies depending on whether a read operation or a write operation is performed. The result is a decoding signal where each cycle represents either a read operation or a write operation, but not both.